Paper Info
Title
BACH: A Bandwidth-Aware Hybrid Cache Hierarchy Design with Nonvolatile Memories.
Abstract
Limited main memory bandwidth is becoming a fundamental performance bottleneck in chipmultiprocessor (CMP) design. Yet directly increasing the peak memory bandwidth can incur high cost and power consumption. In this paper, we address this problem by proposing a memory, a bandwidth-aware reconfigurable cache hierarchy, BACH, with hybrid memory technologies. Components of our BACH design include a hybrid cache hierarchy, a reconfiguration mechanism, and a statistical prediction engine. Our hybrid cache hierarchy chooses different memory technologies with various bandwidth characteristics, such as spin-transfer torque memory (STT-MRAM), resistive memory (ReRAM), and embedded DRAM (eDRAM), to configure each level so that the peak bandwidth of the overall cache hierarchy is optimized. Our reconfiguration mechanism can dynamically adjust the cache capacity of each level based on the predicted bandwidth demands of running workloads. The bandwidth prediction is performed by our prediction engine. We evaluate the system performance gain obtained by BACH design with a set of multithreaded and multiprogrammed workloads with and without the limitation of system power budget. Compared with traditional SRAM-based cache design, BACH improves the system throughput by 58% and 14% with multithreaded and multiprogrammed workloads respectively.
Year
DOI
Venue
2016
10.1007/s11390-016-1609-7
J. Comput. Sci. Technol.
Keywords
Field
DocType
memory bandwidth, hybrid cache, reconfigurable cache, nonvolatile memory
Cache-oblivious algorithm,Cache pollution,CPU cache,Cache,Computer science,Cache-only memory architecture,Real-time computing,Cache algorithms,Page cache,Cache coloring,Embedded system
Journal
Volume
Issue
ISSN
31
1
1860-4749
Citations 
PageRank 
References 
0
0.34
29
Authors
4
Name
Order
Citations
PageRank
Jishen Zhao163838.51
Cong Xu2115448.25
Tao Zhang340219.22
Yuan Xie46430407.00