Name
Title | ||
|---|---|---|
An Energy-Efficient 24t Flip-Flop Consisting Of Standard Cmos Gates For Ultra-Low Power Digital Vlsis |
Abstract | ||
|---|---|---|
In this paper, we propose a low-power circuit-shared static flip-flop ((CSFF)-F-2) for extremely low power digital VLSIs. The (CSFF)-F-2 consists of five static NORs and two inverters (INVs). The (CSFF)-F-2 utilizes a positive edge of a buffered clock signal, which is generated from a root clock, to take data into a master latch and a negative edge of the root clock to hold the data in a slave latch. The total number of transistors is only 24, which is the same as the conventional transmission-gate flip flop (TGFF) used in the most standard cell libraries. SPICE simulations in 0.18-mu m standard CMOS process demonstrated that our proposed (CSFF)-F-2 achieved clock-to-Q delay of 18.3 ns, setup time of 10.0 ns, hold time of 5.5 ns, and power dissipation of 9.7nW at 1-MHz clock frequency and 0.5-V power supply. The physical design area increased by 16% and power dissipation was reduced by 13% compared with those of conventional TGFF. Measurement results demonstrated that our proposed (CSFF)-F-2 can operate at 0.352V with extremely low energy of 5.93 fJ. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1587/transfun.E98.A.2600 | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES |
Keywords | Field | DocType |
D flip-flop, low-power, low-voltage, energy-efficient, compact | Efficient energy use,CMOS,Low voltage,Flip-flop,Electrical engineering,Mathematics | Journal |
Volume | Issue | ISSN |
E98A | 12 | 0916-8508 |
Citations | PageRank | References |
0 | 0.34 | 4 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yuzuru Shizuku | 1 | 7 | 1.59 |
| Tetsuya Hirose | 2 | 183 | 38.44 |
| Nobutaka Kuroki | 3 | 57 | 12.88 |
| Masahiro Numa | 4 | 82 | 20.87 |
| Mitsuji Okada | 5 | 0 | 1.01 |