Title
A Memory-Based Ipv6 Lookup Architecture Using Parallel Index Generation Units
Abstract
In the era of IPv6, since the number of IPv6 addresses rapidly increases and the required speed is more than Giga lookups per second (GLPS), an area-efficient and high-speed IP lookup architecture is desired. This paper shows a parallel index generation unit (IGU) for memory-based IPv6 lookup architecture. To reduce the size of memory in the IGU, we use a linear transformation and a row-shift decomposition. A single-memory realization requires O(2(l) log k) memory size, where l denotes the length of prefix, while the realization using IGU requires O(kl) memory size, where k denotes the number of prefixes. In IPv6 prefix lookup, since l is at most 64 and k is about 340 K, the IGU drastically reduces the memory size. Also, to reduce the cost, we realize the parallel IGU by using both on-chip and off-chip memories. We show a design algorithm for the parallel IGU to store given off-chip and on-chip memories. The parallel IGU has a simple architecture and performs lookup by using complete pipelines those insert the pipeline registers in all the paths. We loaded more than 340 K IPv6 pseudo prefixes on the Xilinx Virtex 6 FPGA with off-chip DDRII+ Static RAMs (SRAMs). Its lookup speed is 1.100 giga lookups per second (GLPS) which is sufficient for the required speed for a next generation 400 Gbps link throughput. As for the normalized area and lookup speed, our implementation outperforms existing FPGA implementations.
Year
DOI
Venue
2015
10.1587/transinf.2014RCP0006
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS
Keywords
Field
DocType
CAM, IP lookup, index generation unit, FPGA
IPv6,Architecture,Computer architecture,Computer science,Field-programmable gate array
Journal
Volume
Issue
ISSN
E98D
2
1745-1361
Citations 
PageRank 
References 
2
0.40
15
Authors
5
Name
Order
Citations
PageRank
Hiroki Nakahara115537.34
Tsutomu Sasao21083141.62
Munehiro Matsuura318924.44
Hisashi Iwamoto4112.28
Yasuhiro Terao520.40