Name
Abstract | ||
|---|---|---|
This paper presents work on integrating wireless 3-D interconnection interface, namely ThruChip Interface (TCI), in three-dimensional field-programmable gate array (3-D FPGA) exploration tool (TPR). TCI is an emerging 3-D IC integration solution because of its advantages over cost, flexibility, reliability, comparable performance, and energy dissipation in comparison to through-silicon-via (TSV). Since the communication bandwidth of TCI is much higher than FPGA internal logic signals, in order to fully utilize its bandwidth, the time-division multiplexing (TDM) scheme is adopted. The experimental results show 25% on average and 58% at maximum path delay reduction over 2-D FPGA when five layers are used in TCI based 3-D FPGA architecture. Although the performance of TCI based 3-D FPGA architecture is 8% below that of TSV based 3-D FPGA on average, TCI based architecture can reduce active area consumed by vertical communication channels by 42% on average in comparison to TSV based architecture and hence leads to better delay and area product. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1587/transele.E98.C.288 | IEICE TRANSACTIONS ON ELECTRONICS |
Keywords | Field | DocType |
TCI, ThruChip, 3-D FPGA, TSV, FPGA, TPR, VPR | Field-programmable gate array,FPGA prototype,Chip,Engineering,Fpga architecture,Embedded system | Journal |
Volume | Issue | ISSN |
E98C | 4 | 1745-1353 |
Citations | PageRank | References |
0 | 0.34 | 8 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Li-Chung Hsu | 1 | 1 | 1.42 |
| Masato Motomura | 2 | 91 | 27.81 |
| Yasuhiro Take | 3 | 95 | 10.24 |
| Tadahiro Kuroda | 4 | 659 | 213.23 |