Name
Title | ||
|---|---|---|
Impact of Write Pulse and Process Variation on 22 nm FinFET-Based STT-RAM Design: A Device-Architecture Co-Optimization Approach. |
Abstract | ||
|---|---|---|
Spin-transfer torque random access memory (STT-RAM) is a promising candidate for universal memory due to its speed, scalability, and non-volatility. A wide range of write speeds from $1$ to $100\,\mathrm {ns}$ have been reported for STT-RAM. As the storage element of an STT-RAM cell, the switching current of magnetic tunnel junction (MTJ) is inversely proportional to the write pulse width. In this... |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/TMSCS.2015.2509960 | IEEE Transactions on Multi-Scale Computing Systems |
Keywords | DocType | Volume |
Switches,FinFETs,Random access memory,Magnetic tunneling,Thermal stability,CMOS integrated circuits | Journal | 1 |
Issue | ISSN | Citations |
4 | 2332-7766 | 5 |
PageRank | References | Authors |
0.45 | 22 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Cong Xu | 1 | 1154 | 48.25 |
| Yang Zheng | 2 | 216 | 33.97 |
| Dimin Niu | 3 | 609 | 31.36 |
| Xiaochun Zhu | 4 | 190 | 9.83 |
| Seung H. Kang | 5 | 139 | 12.36 |
| Yuan Xie | 6 | 6430 | 407.00 |