Name
Title | ||
|---|---|---|
A 5-Gb/s 2.67-mW/Gb/s Digital Clock and Data Recovery With Hybrid Dithering Using a Time-Dithered Delta-Sigma Modulator. |
Abstract | ||
|---|---|---|
A digital clock and data recovery (CDR) employing a time-dithered delta-sigma modulator (TDDSM) is presented. By enabling hybrid dithering of a sampling period as well as an output bit of the TDDSM, the proposed CDR enhances the resolution of digitally controlled oscillator, removes a low-pass filter in the integral path, and reduces jitter generation. Fabricated in a 65-nm CMOS process, the propo... |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/TVLSI.2015.2449866 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | Field | DocType |
Delays,Jitter,Clocks,Noise,Transfer functions,Quantization (signal),Bandwidth | Digitally controlled oscillator,Computer science,Sampling (signal processing),Pseudorandom binary sequence,Delta-sigma modulation,Modulation,Real-time computing,Electronic engineering,Digital clock,Jitter,Dither | Journal |
Volume | Issue | ISSN |
24 | 4 | 1063-8210 |
Citations | PageRank | References |
1 | 0.37 | 15 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Taeho Lee | 1 | 89 | 15.11 |
| Yong-Hun Kim | 2 | 13 | 4.62 |
| Jaehyeong Sim | 3 | 52 | 7.63 |
| Junseok Park | 4 | 214 | 26.80 |
| Lee-Sup Kim | 5 | 707 | 98.58 |