Name
Title | ||
|---|---|---|
Statistical Framework and Built-In Self-Speed-Binning System for Speed Binning Using On-Chip Ring Oscillators. |
Abstract | ||
|---|---|---|
This paper presents a model-fitting framework to correlate the on-chip measured ring-oscillator counts to the chip’s maximum operating speed. This learned model can be included in an auto test equipment (ATE) software to predict the chip speed for speed binning. Such a speed-binning method can avoid the use of applying any functional test and, hence, result in a third-order test time reduction with a limited portion of chips placed into a slower bin compared with the conventional functional-test binning. This paper further presents a novel built-in self-speed-binning system, which embeds the learned chip-speed model with a built-in circuit such that the chip speed can be directly calculated on-chip without going through any offline ATE software, achieving a fourth-order test-time reduction compared with the conventional speed binning. The experiments were conducted based on 360 test chips of a 28-nm, 0.9 V, 1.6-GHz mobile-application system-on-chip. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/TVLSI.2015.2478921 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
System-on-chip,Semiconductor device measurement,Delays,Bayes methods,Frequency measurement,Mathematical model,Linear regression | Oscillation,Test equipment,System on a chip,Bin,Computer science,Operating speed,Real-time computing,Chip,Electronic engineering,Software | Journal |
Volume | Issue | ISSN |
24 | 5 | 1063-8210 |
Citations | PageRank | References |
6 | 0.50 | 17 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Szu-Pang Mu | 1 | 12 | 2.00 |
| Mango C.-T. Chao | 2 | 48 | 7.38 |
| Shi-Hao Chen | 3 | 30 | 6.08 |
| Yiming Wang | 4 | 109 | 28.42 |