Paper Info
Title
Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops
Abstract
The assessment of noise margins and the related probability of failure in digital cells has growingly become essential, as nano-scale MOSFET and FinFET technologies are confronting reliability issues caused by aging mechanisms, such as NBTI and PBTI, and variability in process parameters. The effect of such phenomena on system level operation is particularly related to the Static Noise Margins (in idle and read mode) and the Write Noise Margins of memory elements. While Static Noise Margins have been studied in the past, in this work we calculated and compared the effect of process variations and NBTI/PBTI aging on the Write Noise Margins of various MOSFET- and FinFET-based flip-flop cells. The massive transistor-level Monte Carlo simulations produced both nominal (i.e. mean) values and associated standard deviations of the WNMs of the flip-flops. This allowed calculating the consequent write failure probability as a function of an input voltage shift, and assessing a comparison for robustness among different circuit topologies and technologies. Temperature and voltage dependence is also included in the analysis.
Year
DOI
Venue
2015
10.1016/j.microrel.2015.07.050
Microelectronics Reliability
Keywords
Field
DocType
Digital VLSI,MOSFET,FinFETs,Noise margins,NBTI aging,PBTI aging,Process variations,Setup time slack
Monte Carlo method,FLOPS,Voltage,Electronic engineering,Robustness (computer science),Network topology,Engineering,Noise (radio),MOSFET,Electrical engineering,Standard deviation
Journal
Volume
Issue
ISSN
55
12
0026-2714
Citations 
PageRank 
References 
4
0.43
24
Authors
3
Name
Order
Citations
PageRank
Usman Khalid151.12
Antonio Mastrandrea2236.24
Mauro Olivieri338536.09