Name
Abstract | ||
|---|---|---|
The measurement of static test parameters for an analog-todigital converter (ADC) requires a large volume of test data, especially for a high-resolution ADC. This paper proposes a reduced-code test method for pipelined ADCs that does not compromise test accuracy. The proposed method calculates fault information at each stage by using sub-histograms. The simulation results based on 12-bit pipelined ADCs show a maximum integral nonlinearity error of 0.590 LSB with only 3.92% of the codes required for the conventional histogram-based method. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1587/elex.12.20150417 | IEICE ELECTRONICS EXPRESS |
Keywords | Field | DocType |
analog-to-digital converter (ADC), pipelined ADC, histogram-based test, reduced-code test | Flight dynamics (spacecraft),Histogram,Integral nonlinearity,Test method,Static testing,Computer science,Electronic engineering,Test data,Successive approximation ADC,Least significant bit | Journal |
Volume | Issue | ISSN |
12 | 12 | 1349-2543 |
Citations | PageRank | References |
0 | 0.34 | 4 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hyeonuk Son | 1 | 1 | 1.45 |
| Jaewon Jang | 2 | 1 | 1.38 |
| Heetae Kim | 3 | 0 | 0.34 |
| Sungho Kang | 4 | 436 | 78.44 |