Name
Abstract | ||
|---|---|---|
The efficacy of single instruction, multiple data (SIMD) architectures is limited when handling divergent control flows. This circumstance results in SIMD fragments using only a subset of the available lanes. We propose an iteration interleaving--based SIMD lane partition (IISLP) architecture that interleaves the execution of consecutive iterations and dynamically partitions SIMD lanes into branch paths with comparable execution time. The benefits are twofold: SIMD fragments under divergent branches can execute in parallel, and the pathology of fragment starvation can also be well eliminated. Our experiments show that IISLP doubles the performance of a baseline mechanism and provides a speedup of 28p versus instruction shuffle. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1145/2847253 | TACO |
Keywords | Field | DocType |
SIMD,iteration interleaving,vector iteration,SIMD lane partition,instruction shuffle | Multiple data,Computer science,Parallel computing,SIMD,Real-time computing,Execution time,Partition (number theory),Interleaving,Speedup | Journal |
Volume | Issue | ISSN |
12 | 4 | 1544-3566 |
Citations | PageRank | References |
1 | 0.36 | 14 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yaohua Wang | 1 | 44 | 14.23 |
| Dong Wang | 2 | 1351 | 186.07 |
| Shuming Chen | 3 | 138 | 38.21 |
| Zonglin Liu | 4 | 1 | 0.70 |
| Shenggang Chen | 5 | 21 | 5.98 |
| Xiaowen Chen | 6 | 14 | 8.86 |
| Xu Zhou | 7 | 221 | 41.36 |