Name
Abstract | ||
|---|---|---|
Control-intensive kernels are becoming the bottleneck that limits the performance of Coarse-Grained Reconfigurable Architecture. Some methods, such as predicated execution, speculative execution, and dual-issue-single-execution, have been proposed to alleviate this problem. But they cannot be always efficient for various control flows. This paper proposes a new architecture, which combines the techniques of triggered instruction and parallel condition, in order to solve the problem completely. The architecture utilizes the basic framework of the triggered instruction to avoid over-serialized execution and branch instruction. Meanwhile, it takes the mechanism of the parallel condition to explore the parallelism between predicate and compute instructions without reconciliation operations. The mechanism of executing multiple instructions that have internal control dependence in parallel is discussed as well. The experiment result shows that the proposed architecture can achieve 20.9% to 140.0% higher performance than that of triggered instruction architecture in terms of cycle count. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1145/2744769.2744789 | DAC |
Keywords | Field | DocType |
Reconfigurable computing, triggered instruction, predicate execution, control flow | Bottleneck,Architecture,Dataflow architecture,Speculative execution,Computer science,Control flow,Parallel computing,Transport triggered architecture,Cycle count,Real-time computing,Reconfigurable computing,Embedded system | Conference |
ISSN | Citations | PageRank |
0738-100X | 2 | 0.36 |
References | Authors | |
7 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Junbin Wang | 1 | 3 | 1.73 |
| leibo liu | 2 | 816 | 116.95 |
| Jianfeng Zhu | 3 | 21 | 7.02 |
| shouyi yin | 4 | 579 | 99.95 |
| Shaojun Wei | 5 | 555 | 102.32 |