Name
Abstract | ||
|---|---|---|
This paper presents a new method to design digital circuits for low pattern counts, one of the key factors shaping cost-effective VLSI test schemes. The method identifies the largest conflicts between internal signals that prevent efficient test compaction in ATPG. These locations are modified by inserting conflict-reducing test points (CRTP) to significantly reduce the ATPG-produced pattern counts. Experimental results obtained for large industrial designs with on-chip test compression demonstrate, on average, 3x -- 4x reduction in stuck-at and transition patterns and 3x shorter ATPG times. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1145/2744769.2744817 | DAC |
Keywords | Field | DocType |
Design for testability, scan-based test, test data compression | Design for testing,Automatic test pattern generation,Digital electronics,Fault coverage,Computer science,Test compaction,Test data compression,Electronic engineering,Real-time computing,Vlsi test,Test compression | Conference |
ISSN | Citations | PageRank |
0738-100X | 2 | 0.37 |
References | Authors | |
17 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Haluk Konuk | 1 | 94 | 9.93 |
| Elham Moghaddam | 2 | 79 | 7.05 |
| Nilanjan Mukherjee | 3 | 801 | 57.26 |
| Janusz Rajski | 4 | 2460 | 201.28 |
| Deepak Solanki | 5 | 2 | 0.37 |
| Jerzy Tyszer | 6 | 838 | 74.98 |
| Justyna Zawada | 7 | 20 | 3.48 |