Paper Info
Title
SEU sensitivity and modeling using pico-second pulsed laser stimulation of a D Flip-Flop in 40 nm CMOS technology
Abstract
This paper presents the design of a CMOS 40 nm D Flip-Flop cell and reports the laser fault sensitivity mapping both with experiments and simulation results. Theses studies are driven by the need to propose a simulation methodology based on laser/silicon interactions with a complex integrated circuit. In the security field, it is therefore mandatory to understand the behavior of sensitive devices like D Flip-Flops to laser stimulation. In previous works, Roscian et al., Sarafianos et al., Lacruche et al. or Courbon et al. studied the relations between the layout of cells, its different laser-sensitive areas and their associated fault model using laser pulse duration in the nanosecond range. In this paper, we report similar experiments carried out using a shorter laser pulse duration (30 ps instead of 50 ns). We also propose an upgrade of the simulation model they used to take into account laser pulse durations in the picosecond range on a logic gate composed of a large number of transistors for a recent CMOS technology (40 nm).
Year
DOI
Venue
2015
10.1109/DFT.2015.7315158
2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)
Keywords
Field
DocType
D Flip-Flop cell,Hardware Security,Photoelectric Laser Stimulation,Single Event Effects,Laser Fault Injection,Electrical Modeling
Logic gate,Semiconductor device modeling,Computer science,CMOS,Electronic engineering,Laser,Pulse duration,Flip-flop,Transistor,Integrated circuit
Conference
ISSN
Citations 
PageRank 
1550-5774
1
0.43
References 
Authors
9
6
Name
Order
Citations
PageRank
Clement Champeix1212.97
Nicolas Borrel2213.31
Jean-Max Dutertre331329.14
Bruno Robisson434422.03
Mathieu Lisart5396.01
Alexandre Sarafianos6686.96