Name
Abstract | ||
|---|---|---|
This paper presents a simple BIST enhancement to detect counterfeit circuits which experience aging delays. The approach is based on the NBTI aging factor. HSPICE simulations on 45nm and 65nm technologies using a predictive NBTI degradation model are presented. The results indicate that counterfeit circuits undergone minimal stress are detected consistently in the presence of process variations. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/DFT.2015.7315148 | 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) |
Keywords | Field | DocType |
BIST approach,counterfeit circuit detection,NBTI degradation,aging delay,NBTI aging factor,HSPICE simulation,negative bias temperature instability,built-in-self-test,size 45 nm,size 65 nm | Logic gate,Computer science,Degradation (geology),Electronic engineering,Electronic circuit,Counterfeit,Benchmark (computing),Built-in self-test | Conference |
ISSN | Citations | PageRank |
1550-5774 | 1 | 0.37 |
References | Authors | |
8 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Puneet Ramesh Savanur | 1 | 1 | 0.71 |
| Phaninder Alladi | 2 | 1 | 0.37 |
| Spyros Tragoudas | 3 | 625 | 88.87 |