Name
Abstract | ||
|---|---|---|
To efficiently use multicore processors we need to ensure that almost all data communication stays on chip, i.e., The bits moved between tasks executing on different processor cores do not leave the chip. Different forms of on-chip communication are supported by different hardware mechanism, e.g., Shared caches with cache coherency protocols, core-to-core networks-on-chip, and shared scratchpad memories. In this paper we explore the different hardware mechanism for on-chip communication and how they support or favor different models of communication. Furthermore, we discuss the usability of the different models of communication for real-time systems. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/ISORCW.2015.57 | 2015 IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops |
Keywords | Field | DocType |
multicore communication,real-time systems,time-predictable systems | Computer architecture,Computer science,Usability,Real-time computing,Models of communication,Chip,Multi-core processor,Cache coherence | Conference |
Citations | PageRank | References |
2 | 0.39 | 30 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Martin Schoeberl | 1 | 26 | 2.40 |
| Rasmus Bo Sørensen | 2 | 59 | 5.51 |
| Sparso, J. | 3 | 133 | 104.88 |