Name
Abstract | ||
|---|---|---|
Current pre-silicon verification techniques can not guarantee error free designs for complex integrated circuits during their first fabrication. Some errors are only uncovered when the device is running at full clock speed. Using post-silicon debug techniques, the designer can monitor the device capturing errors that occur only after millions of clock cycles. However, in order to identify the cause of the error, the signals must be stored in a trace buffer memory, dumped, and then analyzed. Thus, the trace buffer size limits the number of analyzed signals, forcing the designer to select a signal subset to monitor from all tapped signals. In this paper, we propose a novel asymmetric network, based on the traditional Omega Network. We propose to use this network as an interconnection fabric to connect the monitored signals to the trace buffer. We compare the Asymmetric Omega Network performance to the Mux Tree Network, which is adopted by industry as the standard solution to interconnect signals for post-silicon debug. We show that our Asymmetric Omega Network is ≈ 4.6 times more effective reducing the blocking rate at the cost of ≈ 21% area overhead compared to Mux Trees. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1145/2800986.2801011 | SBCCI |
Keywords | Field | DocType |
Verification, Trace-Based Debug, Interconnection Network | Observability,Computer science,Multiplexer,Electronic engineering,Real-time computing,Omega network,Interconnection,Integrated circuit,Clock rate,Tree network,Debugging | Conference |
Citations | PageRank | References |
0 | 0.34 | 17 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| André B. M. Gomes | 1 | 0 | 0.34 |
| Fredy A. M. Alves | 2 | 0 | 0.34 |
| Ricardo Ferreira | 3 | 49 | 13.81 |
| José Augusto Miranda Nacif | 4 | 29 | 8.44 |