| TRAVERSAL: A Fast and Adaptive Graph-based Placement and Routing for CGRAs | 1 | 0.35 | 2021 |
| Reshape: A Run-Time Dataflow Hardware-Based Mapping For Cgra Overlays | 0 | 0.34 | 2021 |
| Google Colab Cad4u: Hands-On Cloud Laboratories For Digital Design | 0 | 0.34 | 2021 |
| You Only Traverse Twice: A Yott Placement, Routing, And Timing Approach For Cgras | 0 | 0.34 | 2021 |
| Nmlib: A Nanomagnetic Logic Standard Cell Library | 0 | 0.34 | 2021 |
| HAMBug: A Hybrid CPU-FPGA System to Detect Race Conditions | 0 | 0.34 | 2021 |
| Is it time to include High-Level Synthesis design in Digital System Education for Undergraduate Computer Engineers? | 0 | 0.34 | 2021 |
| A Design Exploration of Scalable Mesh-based Fully Pipelined Accelerators | 0 | 0.34 | 2020 |
| GA-lapagos, an open-source c framework including a python-based system for data analysis | 0 | 0.34 | 2020 |
| Mind the Gap: Bridging Verilog and Computer Architecture | 0 | 0.34 | 2020 |
| On the Impact of the Synchronization Constraint and Interconnections in Quantum-dot Cellular Automata | 2 | 0.40 | 2020 |
| Ropper: a placement and routing framework for field-coupled nanotechnologies | 1 | 0.36 | 2019 |
| READY: A Fine-Grained Multithreading Overlay Framework for Modern CPU-FPGA Dataflow Applications | 0 | 0.34 | 2019 |
| ADD: Accelerator Design and Deploy - A tool for FPGA high-performance dataflow computing. | 0 | 0.34 | 2019 |
| Lessons Learned On Which Applications Benefit When Implemented On Cpu-Fpga Heterogeneous System | 0 | 0.34 | 2018 |
| From Java to FPGA: An Experience with the Intel HARP System | 0 | 0.34 | 2018 |
| Simplifying Hw/Sw Integration To Deploy Multiple Accelerators For Cpu-Fpga Heterogeneous Platforms | 0 | 0.34 | 2018 |
| A GPU/FPGA-Based K-Means Clustering Using a Parameterized Code Generator | 0 | 0.34 | 2018 |
| Minimum Switching Networks | 0 | 0.34 | 2018 |
| Fast analysis of upstream features on spatial networks (GIS cup). | 0 | 0.34 | 2018 |
| Designing a collision detection accelerator on a heterogeneous CPU-FPGA platform | 2 | 0.39 | 2017 |
| SMT-based context-bounded model checking for CUDA programs. | 0 | 0.34 | 2017 |
| Exploring the dynamics of large-scale gene regulatory networks using hardware acceleration on a heterogeneous CPU-FPGA platform | 2 | 0.39 | 2017 |
| A Dynamic Modulo Scheduling with Binary Translation: Loop optimization with software compatibility | 0 | 0.34 | 2016 |
| Verifying CUDA programs using SMT-based context-bounded model checking. | 5 | 0.45 | 2016 |
| A Placement and routing algorithm for Quantum-dot Cellular Automata. | 3 | 0.44 | 2016 |
| SBESC 2014 guest editors' introduction. | 0 | 0.34 | 2016 |
| Be a simulator developer and go beyond in computing engineering | 0 | 0.34 | 2015 |
| SBESC 2013 guest editor’s introduction | 0 | 0.34 | 2015 |
| Vericonn: a tool to generate efficient interconnection networks for post-silicon debug | 0 | 0.34 | 2015 |
| Increasing Observability in Post-Silicon Debug Using Asymmetric Omega Networks | 0 | 0.34 | 2015 |
| A just-in-time modulo scheduling for virtual coarse-grained reconfigurable architectures | 5 | 0.45 | 2013 |
| An FPGA-based heterogeneous coarse-grained dynamically reconfigurable architecture | 11 | 0.73 | 2011 |
| A low cost and adaptable routing network for reconfigurable systems | 4 | 0.43 | 2009 |
| A Polynomial Placement Algorithm for Data Driven Coarse-Grained Reconfigurable Architectures | 8 | 0.51 | 2007 |
| Data-driven regular reconfigurable arrays: design space exploration and mapping | 3 | 0.40 | 2005 |
| An Environment for Exploring Data-Driven Architectures | 2 | 0.40 | 2004 |
