Name
Abstract | ||
|---|---|---|
Cool mega array-SOTB-2 (CMA-SOTB-2) is an ultra-low energy coarse grained reconfigurable architecture (CGRA) for advanced sensor networks, the Internet of Things, and wearable computing. It uses a large processing element (PE) array with combinatorial circuits and a micro-controller for data transfer between data memory and the PE array. To improve the energy efficiency of the previous prototype, the CMA-SOTB, the performance of the micro-controller was improved by introducing parallel data memory access with data manipulators and optimization of both instruction sets and micro-architecture. A delay learning mechanism that finds the optimal delay time for the computation in the PE array is also introduced. Standard cell libraries of the 65nm silicon on thin buried oxide (SOTB) process have been optimized for under-milliwatt operation. A real chip evaluation shows that more than 250-MOPS performance was achieved with only a 0.4-mW power budget by independently controlling the body-bias voltage for the micro-controller and the PE array. The energy efficiency is almost double that of the previous prototype, the CMA-SOTB. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/ReConFig.2015.7393280 | 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig) |
Keywords | Field | DocType |
ultra low power coarse-grained reconfigurable accelerator,CMA-SOTB-2,cool mega array-SOTB-2,ultra-low energy coarse grained reconfigurable architecture,CGRA,advanced sensor networks,Internet of Things,wearable computing,large processing element array,PE array,combinatorial circuits,microcontroller,data transfer,energy efficiency,parallel data memory access,data manipulators,optimization,instruction sets,microarchitecture,delay learning mechanism,optimal delay time,standard cell libraries,silicon on thin buried oxide,under-milliwatt operation,real chip evaluation,body-bias voltage,size 65 nm | Power budget,Data transmission,Computer science,Instruction set,Efficient energy use,Real-time computing,Chip,Standard cell,Electronic circuit,Wireless sensor network,Embedded system | Conference |
ISSN | Citations | PageRank |
2325-6532 | 1 | 0.39 |
References | Authors | |
6 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Koichiro Masuyama | 1 | 7 | 2.69 |
| Yu Fujita | 2 | 16 | 3.60 |
| Hayate Okuhara | 3 | 11 | 5.98 |
| Hideharu Amano | 4 | 1375 | 210.21 |