Hayate Okuhara - Citegraph

Author Info

Name	Affiliation	Papers
HAYATE OKUHARA	Dept. of ICS, Keio University, Yokohama, Japan	16
Collaborators	Citations	PageRank
24	11	5.98
Referers	Referees	References
13	248	80

Search Limit

100248

Publications (16 rows)

Collaborators (24 rows)

Referers (13 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Real Chip Performance Evaluation on Through Chip Interface IP for Renesas SOTB 65nm Process	0	0.34	2019
A Preliminary Evaluation of Building Block Computing Systems	0	0.34	2019
Real Chip Evaluation Of A Low Power Cgra With Optimized Application Mapping	2	0.46	2018
Optimization Of Body Biasing For Variable Pipelined Coarse-Grained Reconfigurable Architectures	1	0.40	2018
Design automation methodology of a critical path monitor for adaptive voltage controls	0	0.34	2018
Adaptive Body Bias Control Scheme for Ultra Low-Power Network-on-Chip Systems	0	0.34	2018
Analysis Of Body Bias Control Using Overhead Conditions For Real Time Systems: A Practical Approach	0	0.34	2018
Glitch-aware variable pipeline optimization for CGRAs	1	0.40	2017
Leveraging asymmetric body bias control for low power LSI design	0	0.34	2017
Multi-objective Optimization for Application Mapping and Body Bias Control on a CGRA	0	0.34	2017
Body Bias Domain Partitioning Size Exploration For A Coarse Grained Reconfigurable Accelerator	0	0.34	2017
Variable pipeline structure for Coarse Grained Reconfigurable Array CMA	1	0.36	2016
Body bias grain size exploration for a coarse grained reconfigurable accelerator	3	0.47	2016
Power Optimization Considering the Chip Temperature of Low Power Reconfigurable Accelerator CMA-SOTB.	2	0.46	2015
A 297mops/0.4mw ultra low power coarse-grained reconfigurable accelerator CMA-SOTB-2	1	0.39	2015
7MOPS/lemon-battery image processing demonstration with an ultra-low power reconfigurable accelerator CMA-SOTB-2	0	0.34	2015

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