Name
Abstract | ||
|---|---|---|
Asynchronous circuits offer promise in handling current and future technology scaling challenges. Unfortunately, their impact has been limited by the lack of design automation. We present A-NTUPLACE, a timing-driven placer uniquely suited to handling quasi delay-insensitive circuits. Our tool uses a generalization of repetitive event rule systems to identify critical signal transitions. The cell placement engine, based on a leading academic placer, NTUPlace3, incorporates net weights to minimize critical wire lengths as well as a novel balancing scheme to ensure isochronic fork constraints are met. We show that our placer is effective at both prioritizing selected nets and balancing forks, demonstrating improvements in 3 of our 4 benchmarks. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/ASYNC.2015.16 | 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems |
Keywords | Field | DocType |
Design Automation,Asynchronous Circuits,Optimization | Fork (system call),Asynchronous communication,Logic gate,Asynchronous system,Computer science,Electronic engineering,Electronic design automation,Linear programming,Electronic circuit,Benchmark (computing),Distributed computing | Conference |
ISSN | Citations | PageRank |
1522-8681 | 3 | 0.41 |
References | Authors | |
25 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Robert Karmazin | 1 | 5 | 0.76 |
| Stephen Longfield Jr. | 2 | 16 | 2.14 |
| Carlos Tadeo Ortega Otero | 3 | 34 | 3.13 |
| Rajit Manohar | 4 | 1038 | 96.72 |