Name
Abstract | ||
|---|---|---|
The key to high performance for GPU architecture lies in massive threading to drive the large number of cores and enable overlapping of threading execution. However, in reality, the number of threads that can simultaneously execute is often limited by the size of the register file on GPUs. The traditional SRAM-based register file costs so large amount of chip area that it cannot scale to meet the increasing demand of massive threading for GPU applications. Racetrack memory is a promising technology for designing large capacity register file on GPUs due to its high data storage density. However, without careful deployment of registers, the lengthy shift operation of racetrack memory may hurt the performance. In this paper, we explore racetrack memory for designing high performance register file for GPU architecture. High storage density racetrack memory helps to improve the thread level parallelism, i.e., the number of threads that simultaneously execute. However, if the bits of the registers are not aligned to the ports, shift operations are required to move the bits to the ports. To mitigate the shift operation overhead problem, we develop a register file preshifting strategy and a compile-time managed register mapping algorithm. Experimental results demonstrate that our technique achieves up to 24% (19% on average) improvement in performance for a variety of GPU applications. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/ASPDAC.2016.7427984 | 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC) |
Keywords | Field | DocType |
performance-centric register file design,GPU architecture,massive threading,threading execution,SRAM-based register file,GPU applications,high data storage density,high performance register file,high storage density racetrack memory,thread level parallelism,ports,shift operation overhead problem,register file preshifting strategy,compile-time managed register mapping algorithm | Status register,Computer science,Memory data register,Parallel computing,Register file,Memory address register,Register renaming,Processor register,Memory buffer register,Racetrack memory,Embedded system | Conference |
ISSN | Citations | PageRank |
2153-6961 | 5 | 0.42 |
References | Authors | |
15 | 8 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shuo Wang | 1 | 303 | 54.05 |
| Yun Liang | 2 | 868 | 59.55 |
| Chao Zhang | 3 | 423 | 38.17 |
| Xiaolong Xie | 4 | 146 | 9.07 |
| Guangyu Sun | 5 | 1920 | 111.55 |
| Yongpan Liu | 6 | 1056 | 84.55 |
| Yu Wang | 7 | 2279 | 211.60 |
| Xiuhong Li | 8 | 44 | 4.22 |