Name
Title | ||
|---|---|---|
Learning-based prediction of embedded memory timing failures during initial floorplan design. |
Abstract | ||
|---|---|---|
Embedded memories are critical to success or failure of complex system-on-chip (SoC) products. They can be significant yield detractors as a consequence of occupying substantial die area, creating placement and routing blockages, and having stringent Vccmin and power integrity requirements. Achieving timing-correctness for embedded memories in advanced nodes is costly (e.g., closing the design at multiple (logic-memory) cross-corners). Further, multiphysics (e.g., crosstalk, IR, etc.) signoff analyses make early understanding and prediction of timing (-correctness) even more difficult. With long tool and design closure subflow runtimes, design teams need improved prediction of embedded memory timing failures, as early as possible in the implementation flow. In this work, we propose a learning-based methodology to perform early prediction of timing failure risk given only the netlist, timing constraints, and floorplan context (wherein the memories have been placed). Our contributions include (i) identification of relevant netlist and floorplan parameters, (ii) the avoidance of long Pu0026R tool runtimes (up to a week or even more) with early prediction, and (iii) a new implementation of Boosting with Support Vector Machine regression with focus on negative-slack outcomes through weighting in the model construction. We validate accuracy of our prediction models across a range of “multiphysics” analysis regimes, and with multiple designs and floorplans in 28FDSOI foundry technology. Our work can be used to identify which memories are “at risk”, guide floorplan changes to reduce predicted “risk”, and help refine underlying SoC implementation methodologies. Experimental results in 28nm FDSOI technology show that we can predict Pu0026R slack with multiphysics analysis to within 253ps (average error less than 10ps) using only post-synthesis netlist, constraints and floorplan information. Our predictions are 40% more accurate than the predictions (worst-case error of 358ps and average error of 42ps) of a nonlinear Support Vector Machine model that uses only post-synthesis netlist information. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/ASPDAC.2016.7428008 | ASP-DAC |
Keywords | Field | DocType |
circuit layout,integrated memory circuits,network routing,silicon-on-insulator,support vector machines,system-on-chip,28FDSOI foundry technology,P&R tool,SoC,boosting implementation,embedded memories,embedded memory timing failures,floorplan design,learning based methodology,learning based prediction,multiphysics analysis,negative-slack,size 28 nm,support vector machine regression,system-on-chip | Netlist,Timing failure,Signoff,Multiphysics,Computer science,Design closure,Power integrity,Real-time computing,Electronic engineering,Boosting (machine learning),Floorplan | Conference |
ISSN | Citations | PageRank |
2153-6961 | 8 | 0.57 |
References | Authors | |
11 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wei-Ting Jonas Chan | 1 | 69 | 6.70 |
| Kun Young Chung | 2 | 18 | 3.11 |
| Andrew B. Kahng | 3 | 7582 | 859.06 |
| Nancy D. MacDonald | 4 | 8 | 0.57 |
| Siddhartha Nath | 5 | 240 | 15.01 |