Name
Abstract | ||
|---|---|---|
Program analysis is a highly active area of research, and the capacity and precision of software analyzers is improving rapidly. We investigate the use of modern software verification tools for formal property checking of hardware given in Verilog at register-transfer level. To this end, we translate RTL Verilog into an equivalent word-level ANSI-C program, according to synthesis semantics. The property of interest is instrumented into the Cprogram as an assertion. We subsequently apply three different software verification techniques -- bounded model checking, path-based symbolic simulation and abstract interpretation -- and compare their performance to conventional methods for property verification of hardware designs at net list and register transfer level. Our experimental results indicate that speedups of more than an order of magnitude are possible. To the best of our knowledge, this is the first attempt to perform property verification of hardware IPs given at register-transfer level using software verifiers. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/ISVLSI.2015.107 | 2015 IEEE Computer Society Annual Symposium on VLSI |
Keywords | Field | DocType |
Bounded Model Checking,Formal Verification,Netlist,RTL,Verilog,ANSI-C,Property Verification,Symbolic Simulation,SAT/SMT,Abstract Interpretation,Scalability | Functional verification,Programming language,Intelligent verification,Computer science,Verification,Formal methods,Computer hardware,High-level verification,Software verification and validation,Formal verification,Software verification | Conference |
ISSN | Citations | PageRank |
2159-3469 | 4 | 0.47 |
References | Authors | |
18 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Rajdeep Mukherjee | 1 | 11 | 3.40 |
| Daniel Kroening | 2 | 3084 | 187.60 |
| Thomas F. Melham | 3 | 384 | 35.63 |