Name
Title | ||
|---|---|---|
TSV Placement and Core Mapping for 3D Mesh Based Network-on-Chip Design Using Extended Kernighan-Lin Partitioning |
Abstract | ||
|---|---|---|
Three-dimensional (3D) Network-on-Chip (NoC) based designs can utilize communication in vertical dimension to reduce distance between cores. Vertical connections are best implemented using Through-Silicon-Via (TSV). However, TSV geometry restricts the number of 3D routers in any layer of the die. This work proposes a strategy to select the TSV positions. This has been augmented by developing a core mapping procedure based on the Kernighan-Lin graph bi-partitioning algorithm, improved via an iterative improvement phase. The overall approach shows promising results compared to the existing mapping and TSV placement algorithms. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/ISVLSI.2015.9 | 2015 IEEE Computer Society Annual Symposium on VLSI |
Keywords | Field | DocType |
Network-on-Chip,KL algorithm,TSV placement,Application mapping,3D-NoC | Graph,Polygon mesh,Algorithm design,Computer science,Parallel computing,Network on a chip,Network on chip design,Benchmark (computing) | Conference |
ISSN | Citations | PageRank |
2159-3469 | 1 | 0.35 |
References | Authors | |
13 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kanchan Manna | 1 | 44 | 5.53 |
| Vadapalli Shanmukha Sri Teja | 2 | 1 | 0.35 |
| Santanu Chattopadhyay | 3 | 343 | 44.89 |
| Indranil Sengupta | 4 | 498 | 55.11 |