Name
Abstract | ||
|---|---|---|
Due to the decreasing size of transistors, the probability of transient errors and the variability of the transistor's characteristics in electrical circuits are continuously increasing. These issues demand for techniques to check the robustness of circuits and their behavior under transient faults and variability. We present a conservative algorithm to decide if a transient fault leads to erroneous output of a circuit. Our approach considers logical, timing, and electrical masking as well as variability in the gates. In experiments, we show the runtime of our implementation on the ISCAS-85 benchmarks and compare our approach to precise transistor-level simulations as well as fast logic level analysis. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/ISVLSI.2015.40 | 2015 IEEE Computer Society Annual Symposium on VLSI |
Keywords | Field | DocType |
robustness checking,single event transient,formal verification | Electrical network,Logic gate,Control theory,Computer science,Electronic engineering,Robustness (computer science),AC power,Logic level,Transistor,Electronic circuit,Formal verification | Conference |
ISSN | Citations | PageRank |
2159-3469 | 0 | 0.34 |
References | Authors | |
9 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Niels Thole | 1 | 0 | 1.35 |
| Görschwin Fey | 2 | 238 | 31.41 |
| Alberto García-Ortiz | 3 | 66 | 19.23 |