Name
Abstract | ||
|---|---|---|
A linear delay element is proposed in 0.18 mu m CMOS technology with a power supply of 1.8V. The proposed delay element maintains linearity over a relatively large input voltage range of 1.2V and its delay range (sensitivity) can be tuned through a bias voltage. Its power dissipation is 50 mu W at a clock frequency of 1GHz and its robustness in different process corners has been shown through simulations. Additionally, a 6-bit 107MS/s Fully Digital ADC with 1.2 V input range has been implemented using the proposed delay element. The simplicity of design and functioning of the proposed delay element contributes to its improved power and energy consumption. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/ISVLSI.2015.109 | IEEE Computer Society Annual Symposium on VLSI |
Keywords | Field | DocType |
delay line,linear delay,delay-locked-loop,fully digital ADC,time-based ADC,pulse width modulator | Delay calculation,Delay line oscillator,Comparator,Process corners,Control theory,Delay-locked loop,Delay,Group delay and phase delay,Digital delay line,Electronic engineering,Engineering | Conference |
ISSN | Citations | PageRank |
2159-3469 | 1 | 0.38 |
References | Authors | |
2 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Afshin Seraj | 1 | 1 | 0.38 |
| Mohammad Maymandi-Nejad | 2 | 85 | 13.20 |
| Parvin Bahmanyar | 3 | 1 | 0.72 |
| Manoj Sachdev | 4 | 669 | 88.45 |