Name
Abstract | ||
|---|---|---|
In this paper, we establish a non-trivial duality between tautology and contradiction check to speed up circuit SAT. Tautology check determines if a logic circuit is true in every possible interpretation. Analogously, contradiction check determines if a logic circuit is false in every possible interpretation. A trivial transformation of a (tautology, contradiction) check problem into a (contradiction, tautology) check problem is the inversion of all outputs in a logic circuit. In this work, we show that exact logic inversion is not necessary. We give operator switching rules that selectively exchange tautologies with contradictions, and vice versa. Our approach collapses into logic inversion just for tautology and contradiction extreme points but generates non-complementary logic circuits in the other cases. This property enables computing benefits when an alternative, but equisolvable, instance of a problem is easier to solve than the original one. As a case study, we investigate the impact on SAT. There, our methodology generates a dual SAT instance solvable in parallel with the original one. This concept can be used on top of any other SAT approach and does not impose much overhead, except having to run two solvers instead of one, which is typically not a problem because multi-cores are wide-spread and computing resources are inexpensive. Experimental results show a 25% speed-up of SAT in a concurrent execution scenario. Also, statistical experiments confirmed that our runtime reduction is not of the random variation type. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/ISVLSI.2015.18 | 2015 IEEE Computer Society Annual Symposium on VLSI |
Keywords | Field | DocType |
circuit duality,SAT speed up,nontrivial duality,tautology check,contradiction check,check problem,exact logic inversion,noncomplementary logic circuits,multicores,statistical experiments,random variation type | Boolean function,Tautology (logic),Logic gate,Boolean circuit,Sequential logic,Computer science,Logic optimization,Algorithm,Logic family,Contradiction | Conference |
ISSN | Citations | PageRank |
2159-3469 | 0 | 0.34 |
References | Authors | |
7 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Luca Amarú | 1 | 206 | 28.41 |
| Pierre-Emmanuel Gaillardon | 2 | 355 | 55.32 |
| Alan Mishchenko | 3 | 982 | 84.79 |
| Maciej J. Ciesielski | 4 | 629 | 74.80 |
| Giovanni De Micheli | 5 | 10245 | 1018.13 |