Name
Title | ||
|---|---|---|
Efficient Implementation Of Scan Register Insertion On Integer Arithmetic Cores For Fpgas |
Abstract | ||
|---|---|---|
Scan flip-flop insertion for aiding design for testability invites additional hardware overhead, thereby deteriorating the performance of the circuit. In this paper, we shall demonstrate a novel FPGA based implementation of inserting scan registers in commonly used Finite State Machines and pipelined datapath circuits with no hardware overhead or compromise in performance. All our proposed designs have been realized using a relatively low-level design methodology involving target FPGA family based primitive instantiation, coupled with their constrained placement on the Xilinx FPGA fabric. Implementation results clearly reveal the superiority of our proposed architectures in comparison to equivalent circuits derived through behavioral modeling with respect to area and speed. Additionally, our proposed scan register inserted circuits compare favourably with circuits designed without the scan flip-flops. Coupled with this, lies the ease of an automated generation of the corresponding Hardware Description Language ( HDL) and placement constraints and their portability among other advanced FPGA families from Xilinx. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/VLSID.2016.61 | 2016 29TH INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2016 15TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS (VLSID) |
Keywords | Field | DocType |
design for testability, scan register, counter, universal shift register, adder, carry chain, look-up table | Design for testing,Lookup table,Adder,Computer science,Field-programmable gate array,Finite-state machine,Electronic engineering,Software portability,Equivalent circuit,Hardware description language | Conference |
ISSN | Citations | PageRank |
1063-9667 | 2 | 0.44 |
References | Authors | |
3 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ayan Palchaudhuri | 1 | 11 | 7.67 |
| Anindya Sundar Dhar | 2 | 97 | 26.09 |