Author Info
Name
Affiliation
Papers
AYAN PALCHAUDHURI
Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur, Kharagpur, India
21
Collaborators
Citations 
PageRank 
11
11
7.67
Referers 
Referees 
References 
12
117
72
Search Limit
100117
Title
Citations
PageRank
Year
Speed-area optimized VLSI architecture of multi-bit cellular automaton cell based random number generator on FPGA with testable logic support00.342021
Design Automation for Tree-based Nearest Neighborhood–aware Placement of High-speed Cellular Automata on FPGA with Scan Path Insertion00.342021
Testable Architecture Design for Programmable Cellular Automata on FPGA Using Run-Time Dynamically Reconfigurable Look-Up Tables00.342020
Placement Aware Design and Automation of High Speed Architectures for Tree-Structured Linear Cellular Automata on FPGAs with Scan Path Insertion.00.342020
Primitive Instantiation for Speed-Area Efficient Architecture Design of Cellular Automata based Mageto Logic on FPGA with Built-In Testability00.342020
Fpga Fabric Conscious Design And Implementation Of Speed-Area Efficient Signed Digit Add-Subtract Logic Through Primitive Instantiation00.342019
VLSI Architectures for Jacobi Symbol Computation00.342019
Design and automation of VLSI architectures for bidirectional scan based fault localization approach in FPGA fabric aware cellular automata topologies20.452019
Fault Localization and Testability Approaches for FPGA Fabric Aware Canonic Signed Digit Recoding Implementations00.342019
High Speed FPGA Fabric Aware CSD Recoding with Run-Time Support for Fault Localization10.412018
Redundant Binary to Two's Complement Converter on FPGAs Through Fabric Aware Scan Based Encoding Approach for Fault Localization Support00.342018
Fast Carry Chain Based Architectures for Two's Complement to CSD Recoding on FPGAs.00.342018
Primitive Instantiation Based Fault Localization Circuitry for High Performance FPGA Designs.00.342017
Efficient Automated Implementation of Testable Cellular Automata Based Pseudorandom Generator Circuits on FPGAs.10.372017
Built-In Fault Localization Circuitry for High Performance FPGA Based Implementations.40.532017
Redundant Arithmetic Based High Speed Carry Free Hybrid Adders with Built-In Scan Chain on FPGAs00.342017
Efficient Implementation Of Scan Register Insertion On Integer Arithmetic Cores For Fpgas20.442016
High performance bit-sliced pipelined comparator tree for FPGAs00.342016
Automated Design of High Performance Integer Arithmetic Cores on FPGA00.342015
Highly Compact Automated Implementation Of Linear Ca On Fpgas10.402014
Effect of malicious hardware logic on circuit reliability00.342012