Name
Abstract | ||
|---|---|---|
This paper presents a VCO architecture capable of generating multi-level synchronous control signals. It has been implemented by stacking multiple identical VCOs which reuse the current among themselves and thereby reduces the overall power dissipation. Clock frequency of all the voltage levels can be controlled by a single input. This stacked VCO can be used to generate switch control signals having optimum voltage swings, for multi-phase Switched-Capacitor based DC-DC converters. The design has been implemented in 65 nm, triple-well, bulk CMOS process. The design example utilizes 3.3 V supply to generate perfectly synchronous clock phases in three separate voltage levels, namely, 0V-1.1V, 1.1V-2.2V and 2.2V-3.3V. The VCO provides output frequency ranging from 16 MHz to 150 MHz with a gain (KV CO) of 248 KHz/mV. Simulation results are presented to demonstrate the functionality and robustness of the design. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/VLSID.2016.27 | 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID) |
Keywords | Field | DocType |
current-starved,vco,current-sharing | Dissipation,Computer science,Voltage,Voltage-controlled oscillator,Robustness (computer science),Electronic engineering,Converters,Ranging,Electrical engineering,Clock rate,Stacking | Conference |
ISSN | Citations | PageRank |
1063-9667 | 0 | 0.34 |
References | Authors | |
2 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Samiran Dam | 1 | 5 | 1.12 |
| Pradip Mandal | 2 | 84 | 23.04 |