Name
Abstract | ||
|---|---|---|
Concurrent switching of flip-flops and logic gates produces a current surge in synchronous circuits resulting in power supply noise and integrity issues. It is well known that peak current caused by simultaneous switching can be reduced by clock skew scheduling. It has been shown that this problem may be formulated as an integer linear programming problem. However, such formulation is computationally expensive for designs with large number of flip-flops. In this work, we propose a fast heuristic method to schedule clock skew for reducing peak current. The proposed method is evaluated on ISCAS-89, ITC99 and synthetic benchmark circuits. Results show that the proposed method finds a near-optimal solution within minutes even for the largest benchmark circuits. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/VLSID.2016.24 | 2016 29TH INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2016 15TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS (VLSID) |
Keywords | Field | DocType |
Clock skew, Peak current, Integer Linear Programming | Clock signal,Clock gating,Timing failure,Computer science,Parallel computing,Clock domain crossing,Real-time computing,Electronic engineering,Integer programming,Clock skew,Digital clock manager,Clock angle problem | Conference |
ISSN | Citations | PageRank |
1063-9667 | 2 | 0.40 |
References | Authors | |
6 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Arunkumar Vijayakumar | 1 | 44 | 4.65 |
| Vinay C. Patil | 2 | 31 | 4.81 |
| Sandip Kundu | 3 | 1103 | 137.18 |