Paper Info
Title
Optimizing latency, energy, and reliability of 1T1R ReRAM through appropriate voltage settings
Abstract
Resistive RAM (ReRAM) has fast access time, ultra-low stand-by power and high reliability, making it a viable memory technology to replace DRAM for main memory. The 1-transistor-1-resistor (1T1R) ReRAM array has density comparable to that of a DRAM array and the advantages of lower programming energy and higher reliability compared to the ultrahigh density ReRAM cross-point array. In this paper, we show how circuit operation parameters, such as the pulse amplitude and pulse widths of word-line (WL) voltage, bit-line (BL) voltage, and source-line (SL) voltage can be used to lower latency, lower power and improve reliability. SPICE simulation results demonstrate that appropriate choice of voltage settings can be used to reduce the write latency of the 1T1R cell by 29.4% and reduce write energy by 46.7% over the DRAM cell. Next, we show how the endurance of ReRAM cell can be improved by increasing the ratio between OFF and ON resistances and reducing SL voltage. We find that of these, reducing the SL voltage results in significant improvement in endurance with smaller energy overhead. Next, we evaluate the system-level performance of a 1GB ReRAM and DRAM memory system using CACTI and GEM5. Simulation results using SPEC CPU INT 2006 and DaCapo-9.12 benchmarks show that the ReRAM based main memory can improve IPC by 4.2% and energy by up to 77.8% compared to a DRAM system.
Year
DOI
Venue
2015
10.1109/ICCD.2015.7357125
International Conference on Computer Design
Keywords
Field
DocType
1T1R ReRAM, latency, energy, reliability, IPC, main memory
Dram,Access time,Computer science,Spice,Latency (engineering),Parallel computing,Voltage,Electronic engineering,Pulse-amplitude modulation,CAS latency,Resistive random-access memory
Conference
Citations 
PageRank 
References 
7
0.48
9
Authors
4
Name
Order
Citations
PageRank
Manqing Mao1172.42
Yu Cao22765245.91
Shimeng Yu349056.22
Chaitali Chakrabarti41978184.17