Paper Info
Title
VLSI implementation of high-throughput, low-energy, configurable MIMO detector
Abstract
This work focuses on a multi-core VLSI implementation of a multiple-input multiple-output (MIMO) detector utilizing a sphere-decoding algorithm. A complex-domain node traversal algorithm that achieves similar performance results as that of an exhaustive-search algorithm where every node is checked and sorted is also described. A 4x4, 64-QAM hard-output detector utilizing this VLSI design occupies 98k gates, and achieves near-ML performance with an average throughput of 1.22 Gb/s and an energy/bit of 23 pJ/b on a nominal 1.2 V supply in a 0.13 mu m CMOS process. The hard-output design can be further expanded to provide soft-output capability, and achieves an average throughput of 0.65 Gb/s and reaches 10(-5) BER at an SNR of 19.7 dB.
Year
DOI
Venue
2015
10.1109/ICCD.2015.7357162
International Conference on Computer Design
Keywords
Field
DocType
high-throughput MIMO detector,low-energy configurable MIMO detector,multicore VLSI implementation,multiple-input multiple-output detector,sphere-decoding algorithm,complex-domain node traversal algorithm,64-QAM hard-output detector,VLSI design,CMOS process,soft-output capability,size 0.13 mum,voltage 1.2 V
Tree traversal,Low energy,Computer science,Signal-to-noise ratio,MIMO,Electronic engineering,Real-time computing,Throughput,Detector,Very-large-scale integration,Bit error rate
Conference
Citations 
PageRank 
References 
0
0.34
26
Authors
3
Name
Order
Citations
PageRank
Pierce I.-Jen Chuang111.38
Manoj Sachdev266988.45
Vincent C. Gaudet322625.84