Name
Abstract | ||
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A regression-based design space exploration methodology is proposed that models the impacts of the memory hierarchy and the network-on-chip (NoC) on the overall chip multiprocessor (CMP) performance. Designers cannot explore all possible designs for a NoC without considering interactions with the rest of the uncore, in particular the cache configuration and memory hierarchy which determine the amount and pattern of the traffic on the NoC. The proposed regression model is able to capture the salient design points of the uncore for a comprehensive design space exploration by designing memory and NoC-specific regression models and leveraging recent advances in uncore simulation. To show the utility of our methodology, UncoreRPD, two case studies are presented: i) analyzing and refining regression models for an 8-core CMP and ii) performing a rapid design space exploration to find best performing designs of a NoC-based CMP given area-constraints for CMPs of up to 64 cores. Through these case studies, it is shown that i) simultaneous consideration of the memory and NoC parameters in the NoC design space exploration can refine uncore-based regression models, ii) sampling techniques must consider the dynamic design space of the uncore, and iii) overall, the proposed regression models reduce the amount of simulations required to characterize the NoC design space by up to four orders of magnitude.
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Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/ICCAD.2015.7372593 | International Conference on Computer-Aided Design |
Keywords | Field | DocType |
uncore RPD,rapid design space exploration,regression modeling,regression-based design space exploration methodology,memory hierarchy,network-on-chip,chip multiprocessor performance,CMP performance,cache configuration,comprehensive design space exploration,NoC-specific regression models,uncore simulation,NoC parameters,NoC design space exploration,uncore-based regression models | Memory hierarchy,Computer science,Cache,Parallel computing,Uncore,Multiprocessing,Design methods,Real-time computing,Memory management,Space exploration,Design space exploration,Embedded system | Conference |
ISSN | ISBN | Citations |
1933-7760 | 978-1-4673-8389-9 | 1 |
PageRank | References | Authors |
0.36 | 18 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Karthik Sangaiah | 1 | 14 | 2.61 |
| Mark Hempstead | 2 | 980 | 81.39 |
| Baris Taskin | 3 | 227 | 40.82 |