Name
Abstract | ||
|---|---|---|
In this paper, we present an accurate delay estimation algorithm at the register transfer level. We introduce "resource binding" as an important source of false paths in a register transfer level structure. "Path mismatching" between two path segments may create another type of false paths when the data-path and controller interact. The existence and creation of such paths and their effect in delay analysis are discussed. We also introduce the Propagation Delay Graph (PDG), whose traversal, for ... |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1109/EURDAC.1996.558226 | EURO-DAC |
Keywords | Field | DocType |
RTL-based datapath-controller design,delay analysis,false path exclusion | Logic synthesis,Any-angle path planning,Shift register,Control theory,Datapath,Tree traversal,Propagation delay,Computer science,High-level synthesis,Real-time computing,Theoretical computer science | Conference |
ISBN | Citations | PageRank |
0-8186-7573-X | 3 | 0.45 |
References | Authors | |
18 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| C. Papachristou | 1 | 56 | 5.81 |
| Mehrdad Nourani | 2 | 908 | 84.95 |