Name
Abstract | ||
|---|---|---|
A DLL with a second order duty cycle corrector which consists of a low pass filter and an integrator is presented. This paper shows the analysis and the design of the second order DCC for loop stability and low jitter. The DLL implemented in a 0.13mum CMOS process achieves an output duty error below plusmn1.6% within plusmn25% external input duty error. It has a 29.2 ps peak-to-peak jitter and a 3.8 ps RMS jitter |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/CICC.2005.1568671 | IEEE Custom Integrated Circuits Conference |
Field | DocType | ISBN |
Duty cycle corrector,Control theory,Computer science,Integrator,Cmos process,Electronic engineering,Low-pass filter,Jitter,Low jitter,Loop stability | Conference | 0-7803-9023-7 |
Citations | PageRank | References |
6 | 1.92 | 1 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Byung-Guk Kim | 1 | 53 | 10.29 |
| Oh Kwang-il | 2 | 18 | 5.80 |
| Lee-Sup Kim | 3 | 707 | 98.58 |
| Dae-Woo Lee | 4 | 6 | 1.92 |