Paper Info
Title
A continuous-time ΔΣ modulator with 91dB dynamic range in a 2 MHz signal bandwidth using a dual switched-capacitor return-to-zero DAC
Abstract
DACs based on switched-capacitor feedback are used in CTΔΣMs to achieve low jitter sensitivity. Unfortunately, they all severely compromise the alias rejection of the modulator around multiples of the sampling frequency. We introduce the Dual Switched-Capacitor Return-to-Zero (Dual-SCRZ) DAC, which addresses this problem. It combines the low clock jitter sensitivity of a Switched-Capacitor DAC with the low peak-to-average ratio characteristic of an NRZ DAC. A single-bit continuous-time ΔΣ modulator that uses the Dual-SCRZ technique and opamp-assistance to improve linearity and reduce jitter sensitivity achieves 91/85.1/83dB DR/SNR/SNDR in a 2MHz bandwidth. Operating at a sampling rate of 256MHz in a 0.18μm CMOS process, the CTDSM dissipates 14.8mW from a 1.8V supply.
Year
DOI
Venue
2015
10.1109/ESSCIRC.2015.7313866
ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)
Keywords
Field
DocType
single-bit continuous-time ΔΣ modulator,dual switched-capacitor return-to-zero DAC,switched-capacitor feedback,alias rejection,sampling frequency,clock jitter sensitivity,peak-to-average ratio characteristic,dual-SCRZ technique,opamp-assistance,CMOS process,bandwidth 2 MHz,size 0.18 mum,power 14.8 mW,voltage 1.8 V
Dynamic range,Computer science,Modulation,Electronic engineering,Switched capacitor,Bandwidth (signal processing),Return-to-zero
Conference
ISSN
ISBN
Citations 
1930-8833
978-1-4673-7470-5
0
PageRank 
References 
Authors
0.34
1
2
Name
Order
Citations
PageRank
Amrith Sukumaran1203.58
Shanthi Pavan239187.81