| Simplified Simulation and Measurement of the Signal Transfer Function of a Continuous-Time Pipelined Analog-to-Digital Converter | 0 | 0.34 | 2022 |
| Analysis of RC Time-Constant Variations in Continuous-Time Pipelined ADCs | 0 | 0.34 | 2022 |
| Design of High-Resolution Continuous-Time Delta–Sigma Data Converters With Dual Return-to-Open DACs | 0 | 0.34 | 2022 |
| Systematic Development of CMOS Fixed-Transconductance Bias Circuits | 1 | 0.36 | 2022 |
| Improved Multistage Continuous-Time Pipelined Analog-to-Digital Converters and the Implicit Decimation Property | 0 | 0.34 | 2022 |
| Alias Rejection in CT Delta-Sigma ADCs Using Virtual-Ground-Switched Resistor Feedback | 0 | 0.34 | 2022 |
| Analysis and Design of a 20-MHz Bandwidth Continuous-Time Delta-Sigma Modulator With Time-Interleaved Virtual-Ground-Switched FIR Feedback | 4 | 0.41 | 2021 |
| Continuous-Time Pipelined Analog-to-Digital Converters: A Mini-Tutorial | 3 | 0.45 | 2021 |
| A 28.5 mu W All-Analog Voice-Activity Detector | 0 | 0.34 | 2021 |
| Continuous-Time Incremental Delta-Sigma Modulators With FIR Feedback | 1 | 0.35 | 2021 |
| Unified Analysis, Modeling, and Simulation of Chopping Artifacts in Continuous-Time Delta-Sigma Modulators | 0 | 0.34 | 2020 |
| Analysis and Design of an Audio Continuous-Time 1-X FIR-MASH Delta–Sigma Modulator | 2 | 0.42 | 2020 |
| A 20 MHz Bandwidth Continuous-Time Delta-Sigma ADC Achieving 82.1 dB SNDR and > 00 dB SFDR Using a Time-Interleaved Virtual-Ground-Switched FIR Feedback DAC | 0 | 0.34 | 2020 |
| Design Techniques for High-Resolution Continuous-Time Delta–Sigma Converters With Low In-Band Noise Spectral Density | 2 | 0.44 | 2020 |
| 16.6 An 800mhz-Bw Vco-Based Continuous-Time Pipelined Adc With Inherent Anti-Aliasing And On-Chip Digital Reconstruction Filter | 0 | 0.34 | 2020 |
| An Alternative Approach to Bode’s Noise Theorem | 1 | 0.41 | 2019 |
| Analysis and Design of Cyclic Switched-Capacitor DC-DC Converters | 0 | 0.34 | 2019 |
| Unified Analysis, Modeling, and Simulation of Chopping Artifacts in Continuous-Time Delta-Sigma Modulators | 3 | 0.42 | 2019 |
| Simplified Analysis of Total Integrated Noise in Passive Switched-Capacitor and N-Path Filters | 0 | 0.34 | 2019 |
| Analysis and Design of a Multi-Step Bias-Flip Rectifier for Piezoelectric Energy Harvesting | 2 | 0.37 | 2019 |
| Improved Chopping in Continuous-Time Delta-Sigma Converters Using FIR Feedback and N-Path Techniques. | 0 | 0.34 | 2018 |
| Analysis of the Effect of Source Capacitance and Inductance on $N$ -Path Mixers and Filters. | 4 | 0.42 | 2018 |
| Finite-impulse-response (FIR) feedback in continuous-time delta-sigma converters | 0 | 0.34 | 2018 |
| Improved Chopping in Continuous-Time Delta–Sigma Converters Using FIR Feedback and ${N}$ -Path Techniques | 0 | 0.34 | 2018 |
| Multi-Step Bias-Flip Rectification for Piezoelectric Energy Harvesting. | 0 | 0.34 | 2018 |
| Continuous-Time Delta-Sigma Modulators With Time-Interleaved FIR Feedback. | 2 | 0.64 | 2018 |
| Generalized Analysis of High-Order Switch-RC N-Path Mixers/Filters Using the Adjoint Network. | 0 | 0.34 | 2018 |
| Practical design and simulation techniques for continuous-time ΔΣ converters | 0 | 0.34 | 2018 |
| A 1 Mhz Bandwidth, Filtering Continuous-Time Delta-Sigma Adc With 36 Dbfs Out-Of-Band Iip3 And 76 Db Sndr | 0 | 0.34 | 2018 |
| Generalized Analysis of High-Order Switch-RC $N$ -Path Mixers/Filters Using the Adjoint Network | 2 | 0.41 | 2018 |
| A 9-GS/s 1.125-GHz BW Oversampling Continuous-Time Pipeline ADC Achieving -164-dBFS/Hz NSD. | 4 | 0.55 | 2017 |
| Analysis and Design of Continuous-Time Delta-Sigma Converters Incorporating Chopping. | 14 | 1.28 | 2017 |
| Analysis of Chopped Integrators, and Its Application to Continuous-Time Delta-Sigma Modulator Design. | 4 | 0.69 | 2017 |
| Simplified Unified Analysis of Switched-RC Passive Mixers, Samplers, and N-Path Filters Using the Adjoint Network. | 3 | 0.40 | 2017 |
| Design of Continuous-Time ΔΣ Modulators With Dual Switched-Capacitor Return-to-Zero DACs. | 0 | 0.34 | 2016 |
| 15.4 A 280µW 24kHz-BW 98.5dB-SNDR chopped single-bit CT ΔΣM achieving <10Hz 1/f noise corner without chopping artifacts. | 1 | 0.40 | 2016 |
| Continuous-time ΔΣ modulators with dual switched capacitor resistor DACs | 0 | 0.34 | 2016 |
| A 13.3 mW 60 MHz bandwidth, 76 dB DR 6 GS/s CTΔΣM with time interleaved FIR feedback | 0 | 0.34 | 2016 |
| Outgoing Editorial. | 0 | 0.34 | 2015 |
| Guest Editorial: Next-Generation Delta-Sigma Converters | 0 | 0.34 | 2015 |
| A continuous-time ΔΣ modulator with 91dB dynamic range in a 2 MHz signal bandwidth using a dual switched-capacitor return-to-zero DAC | 0 | 0.34 | 2015 |
| Next-Generation Delta-Sigma Converters: Trends and Perspectives | 6 | 0.51 | 2015 |
| Programmable analog pulse shaping for ultra-wideband applications | 0 | 0.34 | 2015 |
| 29.1 A 5mW CT ΔΣ ADC with embedded 2nd-order active filter and VGA achieving 82dB DR in 2MHz BW | 1 | 0.43 | 2014 |
| Design Techniques for Continuous-Time ΔΣ Modulators With Embedded Active Filtering | 11 | 0.93 | 2014 |
| Interreciprocity in Linear Periodically Time-Varying Networks With Sampled Outputs | 5 | 0.56 | 2014 |
| Characterization Techniques for High Speed Oversampled Data Converters. | 0 | 0.34 | 2014 |
| Design of Lumped-Component Programmable Delay Elements for Ultra-Wideband Beamforming | 1 | 0.35 | 2014 |
| Continuous-Time Delta-Sigma Modulator Design Using the Method of Moments | 10 | 0.97 | 2014 |
| Incoming Editorial | 0 | 0.34 | 2014 |
