Name
Title | ||
|---|---|---|
180.5mbps-8gbps Dll-Based Clock And Data Recovery Circuit With Low Jitter Performance |
Abstract | ||
|---|---|---|
A wide range delay-locked loop (DLL) based clock and data recovery (CDR) circuit including coarse and fine tune blocks is proposed in this paper. The coarse tune block adopts a time to digital converter and digital control delay line to widen the frequency capture range, reduce locking time and prevent the false locking problem. In the fine tune block, a novel phase detector combines the tasks of sampling and charge-pump using half rate clock. Starting-control circuit can ensure CDR takes full use of the delay range provided by voltage control delay line. Moreover, a fully analog DLL technique is applied to exploit the benefits of low skew and jitter performance. The simulation result shows the proposed CDR can cover a wide frequency range from 180.5Mbps to 8Gbps, while the peak-to-peak jitter of recovery clock is 2.7ps at 200Mbps and 1.06ps at 8Gbps. Fabricated in a 65nm CMOS process, this design dissipates 9.9mW and 22.9mW respectively at 200 Mbps and 8Gbps from a 1.2 V supply. |
Year | Venue | Keywords |
|---|---|---|
2015 | 2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | Clock and data recovery (CDR), wide-range, delay-locked loop (DLL), low jitter, time-to-digital converter (TDC) |
Field | DocType | ISSN |
Half Rate,Computer science,Clock domain crossing,Electronic engineering,Clock skew,Synchronous circuit,Jitter,Phase detector,Time-to-digital converter,Asynchronous circuit | Conference | 0271-4302 |
Citations | PageRank | References |
0 | 0.34 | 6 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yuequan Liu | 1 | 0 | 1.69 |
| Yuan Wang | 2 | 17 | 13.39 |
| Song Jia | 3 | 6 | 7.00 |
| zhang | 4 | 10 | 9.77 |