Paper Info
Title
A 10 Gb/S Hybrid Pll-Based Forwarded Clock Receiver In 65-Nm Cmos
Abstract
A 10 Gb/s PLL-based forwarded clock receiver is implemented in 65-nm CMOS technology. The proposed architecture uses a hybrid PLL-based deskew which is combined with a PLL and a DLL. The PLL provides jitter filtering and the DLL performs deskewing by shifting the divided clocks. Since the operating frequency of the DLL is low, the power consumption of the DLL can be reduced. The measurement results show that the rms jitter of the recovered clock is only 576.7 fs which is quite low for a ring-oscillator-based PLL. The receiver chip occupies an active area of 0.0136 mm(2) and consumes 22.1 mW at the data rate of 10 Gb/s.
Year
Venue
Keywords
2015
2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
Forwarded clock receiver, hybrid, ring PLL, DLL, low jitter
Field
DocType
ISSN
Phase-locked loop,Synchronization,Computer science,PLL multibit,Filter (signal processing),CMOS,Chip,Electronic engineering,Jitter,Phase frequency detector
Conference
0271-4302
Citations 
PageRank 
References 
2
0.40
8
Authors
7
Name
Order
Citations
PageRank
Kwanseo Park1229.60
Woo-Rham Bae24014.93
haram ju3114.11
Jinhyung Lee4156.53
Gyu-Seob Jeong5219.00
Yoonsoo Kim612919.27
Deog-Kyoon Jeong7626119.05