Name
Abstract | ||
|---|---|---|
This paper presents a novel analytical delay model to perform fast estimation of signal delay propagation over buffer chain under time-dependent dielectric breakdown (TDDB) aging effect. The proposed model considers all gate-to-drain, gate-to-source and gate-to-bulk breakdowns effects, and relies on accurate modeling of TDDB. In comparison to SPICE simulation, based on BSIM4 transistor model, experimental results have shown an average error of 1.65%, whereas 98% of the cases present an estimation error of at most 5%. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/ISCAS.2015.7168599 | International Symposium on Circuits and Systems |
Keywords | Field | DocType |
circuit reliability, gate delay model, TDDB, time-dependent dielectric breakdown, oxide breakdown, CMOS design | Delay calculation,Logic gate,Transistor model,Dielectric strength,Control theory,Computer science,Spice,Semiconductor device modeling,Aging effect,Electronic engineering,Time-dependent gate oxide breakdown | Conference |
ISSN | Citations | PageRank |
0271-4302 | 0 | 0.34 |
References | Authors | |
10 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Felipe S. Marranghello | 1 | 21 | 6.50 |
| André Inácio Reis | 2 | 134 | 21.33 |
| Renato P. Ribas | 3 | 204 | 33.52 |