Title
Selectable Starting Bit Sar Adc
Abstract
Prior work used least-significant bit first quantization (LSBFQ) to conserve switching energy and comparator bitcycles, but is limited to low activity signals. Furthermore, LSBFQ results in a large bitcycle range in the quantizer. A novel selectable starting bit quantizer (SSBQ) is proposed which starts quantization with neither the MSB nor the LSB, but an intermediate bit chosen for target applications. It is shown that the proposed algorithm reduces bitcycle range in the quantizer compared to LSBFQ, and provides design flexibility for various activity signals. Furthermore, the proposed solution encompasses LSBFQ since it is a specific case of the proposed architecture. For target applications, the proposed solution will save bitcycles in an A/D conversion, as well as switching energy, over the LSBFQ and the merged capacitor switching (MCS) SAR, the most energy-efficient traditional MSB-first SAR.
Year
DOI
Venue
2015
10.1109/ISCAS.2015.7168968
2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
Field
DocType
ISSN
Algorithm design,Capacitor,Comparator,Computer science,Electronic engineering,Amplitude modulation,Successive approximation ADC,Quantization (signal processing),Least significant bit,Bit (horse)
Conference
0271-4302
Citations 
PageRank 
References 
0
0.34
4
Authors
3
Name
Order
Citations
PageRank
Jerry Leung100.68
Allen Waters2305.03
Un-Ku Moon3836140.98