Name
Abstract | ||
|---|---|---|
Hardening the flip-flops and latches is the most straightforward way to improve the soft-error robustness of sequential logic circuits. This paper presents novel pulse-clocked latch based flip-flops that mitigate not just single event upsets (SEUs) but also single event transients (SETs) that are an increasing threat in high performance logic. The design uses triple-mode redundant latches, combined with appropriate clocking to provide redundancy in both space and time. Analysis of the flip-flop operation and immunity to both SEUs and SETs, as well as layout that provides adequate critical node separation to prevent multi-node charge collection failures, are presented. The multi-bit flip-flop macro has been fabricated and tested functional as shift registers on a 90-nm foundry LP process. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/ISCAS.2015.7168758 | International Symposium on Circuits and Systems |
Keywords | Field | DocType |
Flip-Flop, multiple node charge collection, single event transient, single event upset, triple mode redundancy, temporal hardening | Shift register,Sequential logic,Computer science,Robustness (computer science),Electronic engineering,Redundancy (engineering),Macro,Electronic circuit,Flip-flop,Single event upset | Conference |
ISSN | Citations | PageRank |
0271-4302 | 4 | 0.59 |
References | Authors | |
4 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sushil Kumar | 1 | 510 | 54.39 |
| Srivatsan Chellappa | 2 | 22 | 3.45 |
| Lawrence T. Clark | 3 | 155 | 33.27 |