Name
Abstract | ||
|---|---|---|
VHDL programs are often validated by means of test benches constructed from formal system specification. To include real-time properties of VHDL programs, the proposed approach first transforms them to concurrently running network of timed automata and then performs model checking on properties taken from the specification. Counterexamples generated by the model checker are used to form a test bench. The approach is validated by a case study composed of a nontrivial application running on a microprocessor. As presented, the approach enables testing both hardware and software at once. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/COMPSAC.2015.198 | 2015 IEEE 39th Annual Computer Software and Applications Conference |
Keywords | Field | DocType |
model based testing,VHDL programs,test benches,formal system specification,real-time properties,timed automata,model checking,nontrivial application,microprocessor | Formal system,Model checking,Test bench,Computer science,Automaton,Microprocessor,Real-time computing,Model-based testing,Software,VHDL | Conference |
Volume | ISSN | Citations |
3 | 0730-3157 | 0 |
PageRank | References | Authors |
0.34 | 14 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tolga Ayav | 1 | 27 | 5.97 |
| Tugkan Tuglular | 2 | 27 | 12.51 |
| Fevzi Belli | 3 | 42 | 10.02 |