Name
Abstract | ||
|---|---|---|
Argo is a network-on-chip developed for use in a multi-core platform designed specifically for hard real-time applications and it supports message passing across virtual end-to-end channels. Argo implements these channels using time-division-multiplexing (TDM) of the resources in the NOC following a static schedule. This requires some form of global synchrony across the platform. At the same time it is generally accepted that a large chip should employ some form of globally-asynchronous locally-synchronous (GALS) organization. By using asynchronous routers and by rethinking the microarchitecture of the network interfaces we have managed to combine TDM and GALS and obtain a very hardware-efficient implementation of the NOC. The paper gives a brief overview of the Argo NOC and focuses on two important issues: how to safely bring the NOC out of reset and timing analysis of the network of asynchronous routers. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/ECCTD.2015.7300101 | 2015 European Conference on Circuit Theory and Design (ECCTD) |
Keywords | Field | DocType |
network-on-chip,Argo NOC,time division multiplexing,TDM,globally-asynchronous locally-synchronous organization,GALS organization,multicore platform,hard real-time applications,message passing,virtual end-to-end channels,static schedule,global synchrony,asynchronous routers,network interface microarchitecture,very hardware-efficient implementation | Asynchronous communication,Computer science,Communication channel,Chip,Static timing analysis,Argo,Message passing,Microarchitecture,Network interface,Embedded system | Conference |
Citations | PageRank | References |
1 | 0.35 | 5 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Evangelia Kasapaki | 1 | 154 | 6.37 |
| Jens Sparsø | 2 | 453 | 52.97 |