Name
Abstract | ||
|---|---|---|
This research was supported in part by the Semiconductor Research Corporation under contract SRC 95-DP-109, in part by ARPA under contract DABT63-95-C-0069, and by Hewlett-Packard under an equipment grant. A new sequential circuit test generator, ALT-TEST, is described which alternates repeatedly between two phases of test generation. The first phase uses a simulation-based genetic algorithm, while the second phase uses a deterministic algorithm. The fast execution of the first phase combines with the more powerful test sequence generation and redundancy-identification capabilities of the second phase to produce test sets having high fault coverages in low execution times. The effectiveness of the approach is demonstrated on the ISCAS89 sequential benchmark circuits and several synthesized circuits. |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1109/EDTC.1996.494327 | ED&TC |
Field | DocType | ISSN |
Automatic test pattern generation,Sequential logic,Fault coverage,Computer science,Real-time computing,Electronic engineering,Deterministic algorithm,Electronic circuit,Electricity generation,Genetic algorithm,Benchmark (computing) | Conference | 1066-1409 |
ISBN | Citations | PageRank |
0-8186-7423-7 | 18 | 1.34 |
References | Authors | |
24 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Michael S. Hsiao | 1 | 1467 | 132.13 |
| Elizabeth M. Rudnick | 2 | 867 | 76.37 |
| J. H. Patel | 3 | 4577 | 527.59 |