Paper Info
Title
CHO: towards a benchmark suite for OpenCL FPGA accelerators
Abstract
Programming FPGAs with OpenCL-based high-level synthesis frameworks is gaining attention with a number of commercial and research frameworks announced. However, there are no benchmarks for evaluating these frameworks. To this end, we present CHO benchmark suite an extension of CHStone, a commonly used C-based high-level synthesis benchmark suite, for OpenCL. We characterise CHO at various levels and use it to investigate compiling non-trivial software to FPGAs. CHO is work in progress and more benchmarks will be added with time.
Year
DOI
Venue
2015
10.1145/2791321.2791331
IWOCL
Keywords
DocType
Citations 
OpenCL, FPGA, High Level Synthesis, Accelerator
Conference
5
PageRank 
References 
Authors
0.54
15
3
Name
Order
Citations
PageRank
Geoffrey Ndu1321.75
Javier Navaridas220123.58
Mikel Luján354046.40