Paper Info
Title
19.8 A 0.0021mm2 1.82mW 2.2GHz PLL using time-based integral control in 65nm CMOS.
Abstract
Phase-locked loops (PLLs) are de-facto clock generators in analog, digital, RF, and embedded systems to generate a high frequency output clock from a low frequency reference clock. Modern systems-on-chip (SoCs) require many such PLLs that cater to multi-core processors, memories, IO interfaces and power management. A ring-oscillator-based analog charge-pump PLL offers a flexible and power-efficient way to implement such clock multipliers. However, frequency compensation of analog PLLs requires a large loop filter capacitor that occupies significant area. The area penalty is further exacerbated in deep sub-micron CMOS processes due to increasing oscillator gain and gate leakage. For example, a 2GHz PLL in 65nm CMOS requires a 90pF capacitor (R=1kΩ) to achieve 10MHz bandwidth and 70° phase margin. Assuming a capacitor density of 1fF/µm2, a 90pF capacitor occupies an area of 0.09mm2. Digital PLLs (DPLLs) offer an attractive means to eliminate the loop-filter capacitor [1, 2]. However, quantization error added by its loop components degrades the performance in multiple ways. First, it makes the DPLL loop inherently non-linear causing the steady state to be a bounded limit cycle, which manifests as deterministic jitter (DJ) at the PLL output. Second, it introduces conflicting noise bandwidth requirements, which makes it difficult to achieve low jitter in a power efficient manner. For instance, suppressing TDC quantization error by reducing PLL bandwidth increases the DCO phase noise contribution. As a result, DCO power must be increased to lower its noise contribution. This is especially problematic in ring-oscillator-based DPLLs. Finally, a high-resolution digital-to-analog converter (DAC) needed to interface the DLF output to the ring oscillator typically occupies large area and negates some of the area benefits of DPLLs [1, 2]. In view of these drawbacks, we present a PLL architecture that combines the advantages of analog (no quantization error) and digital PLLs (small area and scalability) by using a time-based integral path. The prototype PLL requires neither a high resolution DAC nor a capacitor and fits in 40µm×52µm (0.0021mm2) active area. It achieves 3.8psrms integrated jitter at 2.2GHz and consumes 1.82mW power.
Year
DOI
Venue
2016
10.1109/ISSCC.2016.7418045
ISSCC
Keywords
Field
DocType
CMOS digital integrated circuits,UHF integrated circuits,UHF oscillators,digital phase locked loops,digital-analogue conversion,jitter,phase noise,DAC,DCO phase noise,DPLLs,IO interfaces,SoCs,TDC quantization error suppression,bandwidth 10 MHz,capacitance 90 pF,clock multipliers,de-facto clock generators,deep sub-micron CMOS process,deterministic jitter,digital PLLs,embedded systems,frequency 2.2 GHz,frequency compensation,gate leakage,high frequency output clock,high-resolution digital-to-analog converter,loop filter capacitor,low frequency reference clock,memories,multicore processors,noise bandwidth,oscillator gain,phase margin,phase-locked loops,power 1.82 mW,power management,quantization error,ring-oscillator-based analog charge-pump PLL,size 65 nm,systems-on-chip,time 3.8 ps,time-based integral control,time-based integral path
Phase-locked loop,Computer science,PLL multibit,Phase noise,Electronic engineering,CMOS,Phase margin,Jitter,Electrical engineering,Frequency compensation,Phase frequency detector
Conference
Citations 
PageRank 
References 
0
0.34
3
Authors
6
Name
Order
Citations
PageRank
Junheng Zhu123.48
Romesh Kumar Nandwana24510.36
Guanghua Shu3579.11
Ahmed Elkholy47716.19
Seong Joong Kim5478.95
Pavan Kumar Hanumolu655484.82