Guanghua Shu - Citegraph

Author Info

Name	Affiliation	Papers
GUANGHUA SHU	Univ Illinois, Dept Elect & Comp Engn, 1406 W Green St, Urbana, IL 61801 USA	19
Collaborators	Citations	PageRank
33	57	9.11
Referers	Referees	References
234	193	68

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100234

Publications (19 rows)

Collaborators (33 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A 0.45-0.7 V 1-6 Gb/s 0.29-0.58 pJ/b Source-Synchronous Transceiver Using Near-Threshold Operation.	2	0.39	2018
A 10-Gb/s/ch, 0.6-pJ/bit/mm Power Scalable Rapid-ON/OFF Transceiver for On-Chip Energy Proportional Interconnects.	3	0.41	2018
Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers.	0	0.34	2018
A 12-Gb/s -16.8-dBm OMA Sensitivity 23-mW Optical Receiver in 65-nm CMOS.	2	0.64	2018
A 0.7V time-based inductor for fully integrated low bandwidth filter applications	0	0.34	2017
A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver.	1	0.43	2017
A 0.0021 mm2 1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS.	0	0.34	2017
A 45-75MHz 197-452µW oscillator with 164.6dB FoM and 2.3psrms period jitter in 65nm CMOS.	0	0.34	2017
19.8 A 0.0021mm2 1.82mW 2.2GHz PLL using time-based integral control in 65nm CMOS.	0	0.34	2016
A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition.	12	0.69	2016
23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS.	1	0.36	2016
3.8 A 0.45-to-0.7V 1-to-6Gb/S 0.29-to-0.58pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS	6	0.81	2015
A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS	1	0.39	2015
A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links	4	0.48	2015
15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS	6	0.81	2014
8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS	8	0.67	2014
A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop	11	0.66	2014
A 12-bit 50-MSPS SHA-less opamp-sharing Analog-to-Digital converter in 65nm CMOS	0	0.34	2011
A 0.22 pJ/step subsampling ADC with fast input-tracking sampling and simplified opamp sharing	0	0.34	2010

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