Name
Abstract | ||
|---|---|---|
Several research studies have considered replacing traditional analog PLLs with an all-digital PLL (ADPLL). In such studies, a key topic relates to the resolution and linearity of the TDC. Power-hungry techniques, such as a Vernier delay line (VDL) and a time amplifier (TA) [1,2], have been proposed to improve time resolution. Recently, a digital-to-time converter (DTC) has been employed to enable power reductions of the VDL and TA-based TDCs by minimizing the number of VDLs and TAs [3,4]. However, the nonlinearity of the DTC remains a problem, since it is much larger than the time resolution of the TDCs and becomes a significant source of fractional spur in the ADPLL. In [3], the effect of the nonlinearity is decreased by utilizing a dithering technique at the expense of a long calibration time (u003e 100ms). The DTC requires inherently more calibration effort for full-scale-delay detection and normalization, since the difference between the full-scale delay and the DCO period also increases the fractional spur significantly. On the other hand, time-to-amplitude-conversion-based TDCs may be another candidate for a high-resolution low-power TDC [5]. However, issues surrounding the nonlinearity of the charge pump (CP) and the full-scale-delay detection limit their utility. |
Year | Venue | Field |
|---|---|---|
2016 | ISSCC | Phase-locked loop,Computer science,Linearity,Vernier scale,Electronic engineering,CMOS,Dither,Charge pump,Electrical engineering,Calibration,Amplifier |
DocType | Citations | PageRank |
Conference | 0 | 0.34 |
References | Authors | |
4 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Akihide Sai | 1 | 20 | 8.25 |
| Satoshi Kondo | 2 | 165 | 23.86 |
| Tuan Thanh Ta | 3 | 18 | 6.20 |
| Hidenori Okuni | 4 | 20 | 4.41 |
| Masanori Furuta | 5 | 17 | 4.42 |
| Tetsuro Itakura | 6 | 187 | 33.44 |